> Programmable IPs in our catalog:

Immediate access – Download efpga IP datasheet

> Customized programmable IPs:

– Dimensions and aspect ratio

– Architecture parameters (LUT count and style, routing density…)

– Customization for special constraints (area, performance, power)

– Customization for special design types or use case

> Verilog programmable IP comprising:

– Synthesizable RTL – Constraint files

– ADICSYS compilation software: Acompile

– Bitstream loader & Test program (BIST)

> Possibility to deliver a hard block (GDSII, OpenAccess, Milkyway) for a given design kit.

> Personalized integration into the customers’ project based on specific constraints.