2016 ADICSYS has joined the DEMETER Consortium
A platform to bring the means to European avionic actors to evaluate the multi core concept regarding aeronautic certification. The demonstrator will include an embedded FPGA that will bring a high level of flexibility to implement dedicated logic like interfaces or hardware acceleration engines tightly coupled with the cores.
ADICSYS at DAC 2015 – EDACafé Interview
ADICSYS at DAC 2014 – Chip Estimate IP talks