ADICSYS technology: Synthesizable Programmable Core (SPC) is a soft FPGA IP for ASICs, SOCs and silicon IPs in general.
The great incentive to implement the Synthesizable Programmable Core lies in the reduction of risks associated with errors, specification changes and early adopters' challenges. The development and verification time for critical blocks can be minimized while bring-up and debugging capabilities are enhanced.
In today's complex systems, customizable logic can reveal itself as a key element for end user applications: pin swapping, prototype and test chip, different configuration of co-processing, post silicon debug ...
Fig 1 - example of SPC integration in SOC architecture
SPC advantages and benefits:
> RTL design cycle relief
Works as for stand-alone FPGAs: correct or modify a circuit after production and in the field when a system is in service. Reduce time to market by reduce design (verification) time. Reduce risks of bugs, offers to implement workarounds or extra guaranties.
> ASIC extended life
• Budget for specifications holes
• Possibility to upgrade a device at the transistor/gate level
• “Post silicon ASIC design”
> Focus on the ASIC
• SPC is uniquely based on standard ASIC CAD tools and methods:
- No constraint for the ASIC design flow
- Accepts the induced limitations (area, circuit type)
- Access to: Simulation, Synthesis, Back end, Test (...)
• Immediate consequences:
- Transparent models and verification
- Reduction of cost/delay of the design phase, NRE are reduced
- Flexibility and ease to adapt to special programmable requests
• RTL IP: no need to silicon-proof every new instance
• These embedded FPGAs are built with the exact same technology than the ASIC: extensive use of standard cells
• Full custom design in recent technology nodes comes with high risk and/or high cost.
• Synthesizing our IPs out of existing standard cells takes away most of the physical design constraints since the silicon circuits have already been validated.
• Recent technology nodes, made accessible:
- They reduce the standard to custom cell design gap
- Offer 5 to 10 metal layers: good for FPGAs
• Standard CAD tools have become very powerful
> Total flexibility
• Late in the game decision to use an embedded FPGA is made possible due to reduced block delivery delay
• The scale / Size / Amount of SPCs are flexible variables
• The choice is not driven by aspects of the technology or project strategy and architecture
• Everything happens at the RTL level, every decision remains reversible until Tape-Out